The issue has been root-caused, and there is a solution (or a workaround, if you will).
The culprit turns out to be power management features on the PCIe root ports which the ExpressCard is connected to.
There are two power management features each PCIe port is capable of supporting as per the ASPM (Active State Power Management) specification : L0s (shallow sleep) and L1 (deeper sleep). They are both designed to be entered automatically when the device is active, but idle (hence the name).
By default, the BIOS (at least on the T60 and probably on others), enables the ASPM features during boot enumeration for every root port that has a device behind it.A small side note
: It appears that the "PCI Power Management" option in the BIOS has no effect whatsoever. Maybe on T60 it only affects legacy PCI devices. Or maybe it's a bug. I understand that later models have "PCI Express
Power Management" option in the BIOS - I haven't verified if it has any effect.
However, if the device was not present during boot, and was only plugged in later, the OS (at least XP and/or Fedora 14) will not enable the ASPM on the parent port.
For whatever reason, the Renesas controllers do not play well with L0s. Read speeds suffer as I described above. Since L0s will be enabled if and only if the card was plugged in at boot, this explains exactly the phenomenon.
It is possible to change the ASPM settings on the fly using a utility that can write to PCI Config Space. Examples are RWEverything
or the Linux setpci
utility. A Windows port of the linux utility can be downloaded here
.Note that the L0s needs to be turned off on the parent PCIe port, not on the USB controller itself
. Specifically for the Intel 82801 PCIe Root Port
(what I have on the T60), the relevant PCI config space register is 0x50.By default, the device will come up with the value of 0x50 set to 0x43. According to lspci
, the first bit controls the L0s feature. Writing 0 to it (i.e., changing the register value to 0x42
) will disable L0s, and it appears that it is this exact bit that affects the read speeds. The second bit controls the L1, and seems to have no effect.
For other PCIe root ports, the relevant config address (it is the first byte of the LnkCtl
block) may differ, but lspci
can help you pinpoint it using the -vvv and -xxx parameters. In any case, for the QM57/67 chipsets on later models it seems to be the same offset.
is a command-line utility, it is possible to have it run automatically at startup and disable L0s on the relevant PCIe root port.Another side note
According to this presentation
, L0s is required by the spec, whereas L1 is required specifically for ExpressCards. However, this one
, specifically slide 27, suggests the opposite - L1 must be enabled for all PCIe modules, and for ExpressCard, additionally L0s. The lspci
claims that indeed the latter is what is taking place - L1 is enabled for all root ports - those hosting the ExpressCard, the LAN and the WLAN. L0s is enabled specifically for the ExpressCard root port (and causes the problem). So it looks like the BIOS was implemented according to the guidelines, and it's either the root port or the controller that doesn't play nice with the specification requirements. I might research more into it later, but in the meanwhile I am pleased with the workaround that allows the USB3 controller to work at full speed.