Yikes, that is very small for a L2 (level 2) cache. Let's see if we can clear this up.
Skip ahead a few paragraphs if you already know this. => Stated basically, your computer uses a bus to talk to the bulk of the memory. This bus can be a bit slow, so memory writes and reads to the memory can causes a lag. Back in the day, a PC with "zero wait state" meant that you weren't expending a clock cycle waiting for the goods to come back from main memory. So a L2 cache of faster (and more expensive, because it's faster) memory was put between the processor and the extended memory banks, and this "cache" would act like a quickie mart for data. A few years ago (386, 486 and Pentium days), 512 KB of L2 cache was good. I believe the 486 and Pentium introduced things like on-chip cache and dual-channel processoring. If the processor found the data there, it got it faster, so the computing took less time. In recent years, Intel has put a form of cache memory right on the processor chip (L1 cache(?)), doing sort of the same thing, but I think it also has other purposes.
As an analogy, think of a computer cooking soup. It realizes it needs some celery, chicken stock, pepper, and oregano. If it has to go to the store to get more celery, cooking will be delayed. If the chicken stock is in the pantry, then the delay is much less. And any good cook keeps the spices right by the stove. Grab the pepper grinder and oregano jar, and stir right in.
Silly, I know. Ron White and Preston Gralla do a far better job in their "How ... works" series for Que.
http://tinyurl.com/b7eu7 The "How Computers Work" book was excellent when it first came out, and I'm sure it still is. I used to look forward to White's column each month in PC/COMPUTING.
I'm wondering if this 32KB you're referring to is
on-chip cache, and not L2 cache. Perhaps this page can help clear it up for us...
http://www.thinkwiki.org/wiki/Category:X22
And lo and behold, this page
http://www.thinkwiki.org/wiki/Intel_Mob ... tium_III-M
Indicates that the Pentium III-M has 512 KB L2 cache, and 2x16 KB L1 cache. Clearer now?