T42p motherboard transplant.

[amdaman]

Might have found one of these to put into my T40, got a few questions about tweaking though:

Can it accomodate the fingerprint scanner palmrest if I find one?

Can it run a 533mhz FSB with the pin mod and my 1.7 Dothan?

Can you undervolt it?

Is the stock cooler ok for the t42p? It seems to have some pad on top of the GPU which doesn't seem that good.

Can you change latency of the RAM to 2.0, also is it locked to 400mhz?

I'm not afraid to experiment

[aaa]

I think there's two types of boards, w/ and without the scanner.

No. There is a more complicated 533 mod by member cithrix here.

Yes, you can still undervolt.

No. You need the long fan to cool the GPU.

Not sure, There might be a program who's name escapes me atm to do this. However, you only have a choice of 266 and 333 (unless you do the mentioned 533 mod), and that is usually determined by the SPD of the ram sticks you use.

[sjthinkpader]

...
Can you change latency of the RAM to 2.0, also is it locked to 400mhz?

I'm not afraid to experiment

CL=2 at 400Mhz means tCAC=5nSec. Even the PC2-6400 has tCAC at 7.5nSec. This value hasn't changed over several generations of RAM. As the clock speed got higher, CL got longer and the tCAC is still at 7.5nSec.

A 400Mhz PC3200 works in my T42 but of course it is working at 333Mhz. As speed got higher, the passive components in the signal path became the unmovable obstacles, the MB trace length, skew between signal paths (64 data, 15-16 addresses), DIMM connector, more trace path on DIMM etc.

[aaa]

CL=2 at 400Mhz means tCAC=5nSec. Even the PC2-6400 has tCAC at 7.5nSec. This value hasn't changed over several generations of RAM. As the clock speed got higher, CL got longer and the tCAC is still at 7.5nSec.

Not impossible of course, cuz there's rare cases of as low as 3ns (I personally have a couple of <4ns DDR). There is easily obtainable 5ns desktop DDR2.

You'll have a hard time finding these for a laptop though, they don't sort them out like they do for desktops.

But yeah, they've apparently hit a wall a while ago.


I've remembered the program, it's called WPCREDIT. No idea if it works.

[amdaman]

Hi, i'm not sure what you mean about the memory timings?

Anyway i've just used the RAM utility to adjust memory timings and I got some odd results?

Why is 2.5-3-3-7 FASTER than 2.5-2-2-5?

Theres is about a 10% difference in bandwidth?

I can't adjust the CAS to 2.5 either, not sure why?

The SETFSB program won't work but you can adjust the voltages and the way the CPU loads, which is useful I suppose.

[aaa]

He's saying that by default the CAS isn't faster than 7.5ns for all ram in the end, no matter the mhz. If the program lets you change the CAS then it's irrelevant, as you can try and see if CL2/333 (6ns) works, and whether it does depends on luck. If it's 266 then it usually is CAS2 already as that is 7.5ns.


As for the weird results, maybe the mhz is changing too? Dunno...

[sjthinkpader]

CL=2 at 400Mhz means tCAC=5nSec. Even the PC2-6400 has tCAC at 7.5nSec. This value hasn't changed over several generations of RAM. As the clock speed got higher, CL got longer and the tCAC is still at 7.5nSec.

Not impossible of course, cuz there's rare cases of as low as 3ns (I personally have a couple of <4ns DDR). There is easily obtainable 5ns desktop DDR2.
...

May be you mean cycle time, 333Mhz is 3nSec. 3nSec access from CAS means CL=1 at 333Mhz. There is no such animal...chip.

CL is counted in clock cycles. 333Mhz=3nSec per cycle then:

333Mhz at CL=2.5 means 7.5nSec
400Mhz at CL=3 means 7.5nSec
533Mhz at CL=4 means 7.5nSec
667Mhz at CL=5 means 7.5nSec again.

Once the RAM receives the address of the memory location from the North Bridge (CAS low), it needs time to decode the address, activate the memory cells and get the data to the output buffer. So 7.5 nSec is very hard to decrease. Doesn't matter whether it is for desktop or laptop for this operation. Laptop chips may have the auto refresh enabled, which is only a mode selection.

Once the first data came out, if the next data is in page; next data out is just another cycle for SDR (single data rate) and half cycle for DDR (double data Rate).

Note that tCAC is an old method of measuring RAM timing. But I am just using it to show the first access of RAM had not improved in spite of faster cycle rate for each generation.

[aaa]

There's CL4 DDR2-800.

7.5ns is very hard to decrease for 100% of a giant batch of chips. But if you can afford to pick and choose, then you can try and see how low you can go. Hence the cherrypicked but common CL4/800 ram.

The point is, 7.5ns isn't a hard limit, they just can't guarantee that all of the millions of chips they make can do better.

Anyways, I'm not sure, but the factoring in of the chipset and such is a very different number, that adds up to 50 or 70ns. The 7.5ns is just a small part exclusive to the memory chips.

[sjthinkpader]

There's CL4 DDR2-800.

7.5ns is very hard to decrease for 100% of a giant batch of chips. But if you can afford to pick and choose, then you can try and see how low you can go. Hence the cherrypicked but common CL4/800 ram.
....

So these chips are rated at tCAC=5nSec

They are not selected but by design. You can make the wafer process to yield higher speed with shorter gate length, different doping, lower input capacitance etc. But the yield will be low with more of defects. The product may be more susceptible to ESD etc.

If you test 100 chips and find 2 that are of this speed and sell the rest at normal DRAM prices, you will be out of business for sure.

[sjthinkpader]

There's CL4 DDR2-800.

7.5ns is very hard to decrease for 100% of a giant batch of chips. But if you can afford to pick and choose, then you can try and see how low you can go. Hence the cherrypicked but common CL4/800 ram.

...

Sorry to report more bad news, I didn't have my facts straight. I went back and reviewed Micron's DDR2 datasheet. They are the parent of Crucial and maker of this Ballistix DIMM.

From Micron datasheet (88K file):

DDR2-400 cycle time=5nSec, CL=3, tCAC=15nSec
DDR2-533 cycle time=3.75nSec, CL=4, tCAC=14nSec
DDR2-667 cycle time=3.0nSec, CL=5, tCAC=15nSec
DDR2-667 cycle time=3.0nSec, CL=4, tCAC=12nSec
DDR2-800 cycle time=2.5nSec, CL=5, tCAC=12.5nSec
DDR2-1066 cycle time=1.875nSec, CL=7, tCAC=13.125nSec Speedy

Old Toshiba DRAM (97K file) from ten years ago:
SDR-125 cycle time=8nSec, CL=2, tCAC=16nSec

That Ballistic info is sketchy but:
DDR2-800 cycle time=2.5nSec, CL=4, tCAC=10nSec

Because it is DDR, the 800Mhz is data rate, not clock rate. Clock rate is only 400Mhz, then it gave us 2.5nSec cycle time. As clock rate got faster, the DRAM needed more and more CL. But once the column address is strobed in, the DRAM can pump the data out at 800Mhz rate, which is pretty amazing by itself.

So you can see there is no 3nSec or even 5nSec CAS access DRAM.