T30 ram upgrade - does chip density matter?

[jacksonP]

Greetings. Long-time lurker, first post.

I'm about to order some RAM for my T30, and Crucial recommend this
http://www.crucial.com/store/mpartspecs ... 19A5CA7304
for my T30 2366. But on their site they also had this
http://www.crucial.com/store/partspecs. ... CT6464X335
which seems to be the same spec at a lower price.

I asked them if there was a difference, and they said the latter was a high-density model, and would not work in my T30.

OK, so question 1: Is it true that high-density memory (whatever that means) won't work in a T30, and if so, is there an easy way to tell if memory is regular or high-density?

And question 2: I'm now thinking of going to a 1g card in case of future memory slot failures. Crucial don't recommend any 1g memory for the T30, but based on reading previous posts here, it looks to me like this would be the one:
http://www.crucial.com/store/partspecs. ... T12864X335
Have I got it right? Is that high-density or not (assuming it matters)?

I know there are cheaper sources than Crucial, but I've used Crucial before and they're quick at shipping to Hong Kong. Thanks in advance.

[Harryc]

I have used CT12864X335 in a T30. It worked just fine.

[madkat]

i have this in my T30: http://www.18004memory.com/focus.asp?sku=502430
it works just fine
i don't have two of them because of the failing memory slot

[jacksonP]

Thanks for the fast responses.

madkat, just in case you're ordering RAM anytime soon, 18004memory.com is more expensive than Crucial at the moment ($54 vs $45 for 1gig).

Harryc, that's exactly what I needed to find out, thanks! Much appreciated. I'm ordering the CT12864X335 right now.

I'm still vaguely curious if chip density matters at all, if anyone knows...?

[rkawakami]

"Low" vs "high" density is basically a difference in the DRAM's refresh specification and applies in the situation when talking about the change made during the SDRAM days when designs went from 16MB (aka, low density) to 32MB (high density). I don't believe that there's any difference between 32MB and 64MB DDRAM components that would be on a 512MB PC2100/PC2700 DDR module. From what I remember and quickly looking at some datasheets, both of those component designs use 8K refresh cycles.

With your CT12864X335 module, that should have a total of 8 1Gb components. Those 1Gb parts, possibly Micron MT46V64M16, also have an 8K refresh spec. It would have to in order for your T30 to accept those modules.

[jacksonP]

I'm even more confused about what density means now.

This article http://reviews.ebay.com/Myth-Low-Densit ... 0001236178 suggests something (although I don't totally understand what it means).

Wikipedia says something else again: http://en.wikipedia.org/wiki/DDR_SDRAM# ... ow_Density

And Crucial says something else again. When I asked them if the CT12864X335 was low or high density, they said "low" (good!), and explained that as:
"Low density means that the memory is dual sided, (chips on both sides of the modules). It uses basically two highway paths to transfer information instead of one at a faster rate as in high density. The high density chips only have chips on one side and only one highway to transfer information. "

That seems to contradict both the eBay and Wikipedia articles, and also rkawakami's post. But the bottom line seems to be that yes, density (whatever that actually means) does matter; Low=good, High=bad.

[sjthinkpader]

In the beginning, all memory uses broad side addressing. These are simple addresses numbered A0, A1, A2, A3-An. As memory got larger, the address pin became more and more. In order to cut down on the pin count and cost to package memory; DRAM were designed to receive addresses in two groups, row addresses and column addresses. Row addresses were strobe in first, then column addresses.

JEDEC SIMMs and DIMMs were designed for single bank and double bank versions. The banks are controlled by RAS (row address strobe) and CAS (column address strobe) lines. These are kind of activation signals for the memory.

Low density modules of a particular density usually use 2 RAS lines thus two banks.

High density modules of the same density usually only use 1 RAS as a signle bank. Since this single bank is twice as deep as one bank of a double bank module, it uses one more address than the low density version.

Physically how chips are arranged on the module is not an absolute indication of single bank, double bank, low density or high density.

The PC northbridge chips of a particular generation were designed with a limited number of RAS lines (usually four) and limited number of address lines (12 - 13). If they are short one address line, then high density modules don't work.

I have a Minolta printer that uses a large single bank module. So I had to find a high density, single bank module. When I inserted a double bank module, only half amount of the memory showed up. It took me a while to find these high density, single bank modules for my printers since most sellers can't tell the difference.

Ray is correct that refresh is different between high density and low density because of the difference in the number of addresses to be refreshed. I believe DDR2 and later use self refresh and made it simpler.

[rkawakami]

Over the last couple of years what I've been able to surmise about the use of the term "density" when discussing memory modules is that each person has his/her own definition on what it means to them . When I think of "density", it is referring to the amount of data storage contained within a single memory component on the module. I've seen some people call an 8-chip module "low density" and an identical capacity module that has 16 chips on it "high density", simply because the 8-chip module is less densely packed than the 16-chip version. Prior to getting involved with Thinkpads, I was not aware of these density monikers being used to describe this difference in memory design. As a memory test engineer, all I was concerned with was making sure that test programs were written so that each part was getting properly tested to the datasheet specifications.

As I've been mostly stuck in the PC100/PC133 SDRAM-class systems (600, T2x, X2x), whenever anyone mentions "low vs. high density" I believe that the real difference they are talking about is in the refresh specification between 16MB (128Mbit, or low density) and 32MB (256Mbit; high density) devices.

<Sorry for the long-winded explanation that follows but it's as simplified as I can get it....>

The "D" in SDRAM stands for "dynamic", or "ever changing". Each bit of data in a DRAM is simply a tiny capacitor that either stores a charge or doesn't. By nature, a capacitor this small cannot permanently retain its charge. That means if nothing is done, the charge in each memory cell will eventually decay and therefore change states (from a "zero" to a "one" or vice versa). The amount of time it takes for a memory cell to lose the stored charge is called the "refresh interval". This time is generally in the amount of hundreds of milliseconds (mS) but varies greatly with temperature.

For many years now, the standard refresh interval specification that all SDRAMs must meet is 64mS. This means that in order to guarantee proper functionality of the memory, every single data bit in the memory array must be able to retain its charge for at least 64mS under all operating conditions, without being purposely refreshed. Or put another way, the memory controller inside a computer must refresh each memory cell every 64mS to insure that the memory stays intact. So "refreshing" is basically the act of keeping the data in the memory alive. This is the time-element nature of the refresh specification. Here's the second part...

The memory array is arranged (aka, addressed) as a series of rows and columns. By selecting a row of data in the memory array, all of those data bits in that row are automatically re-charged or refreshed. As SDRAMs were designed with larger and larger array sizes (storage capacity, or "denseness" ), the number of rows or "refresh cycles" increased. In the days of 16MB devices, the number of refresh cycles needed was 4,096 or 4K ("K" represents 1,024). With the first 32MB devices, the number of rows increased to 8,192 or 8K.

When the refresh interval is combined with the number of refresh cycles, you get the total picture. A 16MB SDRAM must receive 4K refresh cycles every 64mS. A 32MB SDRAM must receive 8K cycles within the same 64mS. Expressed in a slightly different way, you must refresh a different row in a 16MB SDRAM every 15.6uS (64mS/4,096), while the 32MB SDRAM needs a refresh cycle every 7.8uS (64mS/8,192).

This is the difference between "low" and "high" density 256MB SDRAM modules as used in PC100 or PC133 systems. The memory controllers inside Thinkpads are designed to generate a certain number of refresh cycles and I don't know if it's possible to make any hardware/firmware changes. If a 600X system only generates 4K refresh cycles every 64mS, you can't expect to use memory components which require twice as many refresh cycles.

Now, when talking about "density" for DDR (double data rate) systems, I don't think that refreshing has anything to do with it. In fact, I would say that most DDR and DDR2 designs now incorporate self-refresh which simplifies matters. From the datasheets that I've quickly looked at, there's no difference in the refresh specifications between 64MB, 256MB or even 512MB devices. In this respect, maybe people are still referring to size of the memory array, but now are talking about the addressing. I can see where there might be a limitation on what the maximum address range that a computer can handle. By using parts which have a smaller number of output pins (i.e., x4 or x8, vs. a x16 part), the address range increases by a factor of 2 or 4. It all depends upon the chipset being used inside the system.

SDRAM references:
download.micron.com/pdf/datasheets/dram/sdram/128msdram.pdf
download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf
download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf

DDRAM references:
download.micron.com/pdf/datasheets/dram/ddr/256MBDDRx4x8x16.pdf
download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf

edit: Now that I see that my neighbor, sjthinkpadder, has snuck in while I was composing another one of my massive posts and brought up another very good point about module construction (i.e., banks), I hope your eyes haven't glazed over .

[alfadog]

Density, as I understand it, always refers the the internal construction of the individual soldered-on chips that make up a piece of memory, the DIMM or SODIMM module that you install in your computer. Here is a visual aid and note that we will talk mainly about bits, not bytes so make sure you keep that in mind (8 bits = 1 byte): Imagine a 64-lane highway full of cars moving in parallel, that is your memory slot. The data will flow between the memory chip and the CPU 64 bits (not bytes) at a time, 64 cars in 64 lanes passing 64 toll booths in parallel. Behind the toll booths the cars are backed up in each lane waiting to get through. There are as many cars backed up as you have memory locations; eg. 8,589,934,592 locations in a gigabyte of RAM but don't think about that, think about 64 lanes of data backed up very deep. If you calculate it out you will see that the traffic is backed up 134,217,728 cars deep. You could say that the total traffic is 134,217,728 x 64 which can also be stated as 128Mx64 where M = 1024x1024 which is a "million" in binary talk. A 1GB module will also be called a 128Mx64 module. All 1GB modules; that tells you nothing about the density. To understand density we are going to break up that huge rectangle of cars behind the toll booths. We are going to break them into sixteen groups which will correspond to the sixteen memory chips on your memory module. There are a number of ways we can break them up but the two common ways are groups of 8 lanes wide by 67,108,864 cars deep (64M deep) or groups of 4 lanes wide by 134,217,728 cars deep (128M deep); 64Mx8 (low density) or 128Mx4 (high density) in memory terminology. Put sixteen of those together and then convert bits to bytes by dividing by 8 and you have your 1GB. And that is all there is to it. Kinda. Another thing to understand is that density is a moving target. When we talk PC100/133 we might say that 8Mx8 is low density or maybe 16Mx8 is but 32Mx8 or 16Mx16 would be high density. Today 32Mx8 would be very low density indeed. The terms are slippery. What you really need to know is what specific memory configurations your computer or chipset will support and what exactly is being used on the module you are looking at. That is where we trust Crucial or Kingston to do the work for us. I will stop here.

Oh, I see I calculated this out for a 1GB module, not the 512MB module you mention. No matter, it is just an example anyway. Your 512MB module would have eight 64Mx8 (low) or 128Mx4 (high) chips, not sixteen.

Hope that helps.
alfadog
ps - that post was medium density

[sjthinkpader]

.... we might say that 8Mx8 is low density or maybe 16Mx8 is but 32Mx8 or 16Mx16 would be high density. Today 32Mx8 would be very low density indeed. The terms are slippery. ...

16Mx8 will need one more address than 8Mx8. So when these two chips are mounted on the same total density modules, the one with 16Mx8 chips will be termed "high density" because it needs one more address than the others.

Likewise, when mounted on same total density modules, 16Mx8 version as compared to 32Mx8 version will be termed "low density".

What makes these things complex are the total number addresses can be split into several row and column address combinations. The older design were always symmetrical: 9 rows/9 columns, 10 rows/10 columns, 11 rows/11 columns etc.

From 2Mx8 (chip) generation, assymmetrical addressing appeared. So 22 total addresses can be 11R/11C or 12R/10C. Systems designed with 11 address lines cannot use these new 12R/10C chips because they are short one address line. Most newer northbridge chips are smart enough to read the SPD (serial presence detect) chip on JEDEC modules to see what chip configurations are mounted and reconfigures the address lines to work with many chip designs.