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Posted: Mon Jan 15, 2007 11:29 am
by brentpresley
Austin_Goh wrote:
When we are talking about dual channel here, it represents theoretically 8400MB/s ( 2*533MHz*64bit/8 ) or
10600MB/s ( 2*667MHz*64bit/8 ).
Your all are right ONLY IF the Core 2 Duo on mobile has 1066MHz or 1333MHz Front Side Bus.
Bottleneck on Current Merom and Upcoming Santa Rosa Core 2 Duo is the CPU Front Side Bus, that's why no matter is 400/533/667/800 it is, as long as dual channel applied, the effective memory bandwidth obtained is about the same, at the same time lower latency RAM would provide performance gain in real life applications.
WRONG WRONG WRONG.
At 1066MHz you can install a kentsfield CPU in a desktop CPU (TWICE as many cores at 4) and it is still not FSB bandwidth limited.
That means a PAIR of cores does not fully utilized the 533MHz FSB, not to mention the 667MHz fsb. ESPECIALLY when you consider that laptop CPUs run at lower speeds and have even LESS bandwidth need. You will see MINIMAL increases in performance from Santa Rosa. Like 1/2 the chipsets that Intel releases it is more a marketing gimmick than anything.
Please do your homework before you come here and spout off this nonsense.
Posted: Mon Jan 15, 2007 11:34 am
by Austin_Goh
What are you talking about?
You try Kentsfield @ 667MHz FSB (if your mainboard allows to), see if it is FSB Limited or not.
Intel will increase FSB of future Core processors to 1333 or even 2000MHz Front Side Bus once faster DDR3 Memory launched.
brentpresley wrote:
WRONG WRONG WRONG.
At 1066MHz you can install a kentsfield CPU in a desktop CPU (TWICE as many cores at 4) and it sit still not bandwidth limited.
That means a PAIR of cores does not fully utilized the 533MHz FSB, not to mention the 667MHz fsb. You will see MINIMAL increases in performance from Santa Rosa.
Please do your homework before you come here and spout off this nonsense.
Posted: Mon Jan 15, 2007 11:37 am
by brentpresley
Simple MATH here.
Kentsfield = 4 cores at 1066MHz FSB. That is 266MHz FSB PER CORE and it is NOT FSB limited.
Core 2 Laptop = 2 cores at 533 or 667MHz FSB. That is 266 or 333MHZ FSB PER CORE. The SAME or MORE than a desktop processor running twice as many cores.
Posted: Mon Jan 15, 2007 11:41 am
by Austin_Goh
First time heard got people said Intel Core processor has divided FSB to use !!! LOL
brentpresley wrote:Simple MATH here boy genius.
Kentsfield = 4 cores at 1066MHz FSB. That is 266MHz FSB PER CORE and it is NOT FSB limited.
Core 2 Laptop = 2 cores at 533 or 667MHz FSB. That is 266 or 333MHZ FSB PER CORE. The SAME or MORE than a desktop processor running twice as many cores.
Do you understand now?
Posted: Mon Jan 15, 2007 11:43 am
by brentpresley
..
Posted: Mon Jan 15, 2007 11:46 am
by Austin_Goh
I can only say you are totally wrong, do a thorough research first on Intel Front Side Bus and the difference with AMD Counterparts which doesn't use Front Side Bus now.
There is no need to prove further to YOU as you can't seem to understand what I explained and also knows nothing to respect people.
brentpresley wrote:That's the BEST reply you have? You can't come up with a LOGICAL retort to the reasoning presented?
LOL.
Posted: Mon Jan 15, 2007 11:48 am
by brentpresley
Austin_Goh wrote:I can only say you are totally wrong, do a thorough research first on Intel Front Side Bus and the difference with AMD Counterparts which doesn't use Front Side Bus now.
There is no need to prove further to YOU as you can't seem to understand what I explained and also knows nothing to respect people.
No such EVIDENCE exists.
Please come back when you have READ up on cache coherency AND memory bandwidth utilization.

Posted: Mon Jan 15, 2007 12:30 pm
by BillMorrow
This is a very interesting discussion..
DO NOT let this thread become a flame war..
on the matter that brought me to this interesting thread, I see some disagreement descending into less than gentlemanly conduct..
please keep it civil here or the supervising moderator will lock this thread again and i will not unlock it twice..
IF there is disagreement, then please post your reference material..
Posted: Mon Jan 15, 2007 2:19 pm
by brentpresley
Let me lay this out in SIMPLE terms:
Cores SHARE FSB bandwidth like cars share lanes on a highway. But each lane is not assigned to a specific car (which you seem to be MISquoting me on).
The lanes ALL go to one place, the MCH (AKA Northbridge, the memory controller hub). The MAJORITY of those lanes go on to the memory modules. A few branch off to the Southbridge that controls peripherals (USB ports, etc.).
Currently, even a 4-core Kentsfield doesn't use up all of 1066MHz on the FSB to access main memory. Not even close. It is ONLY when you significantly overclock these chips to beyond 3.6GHz that you start to see performance that is limited by the FSB. Until then, there are are more than enough "lanes" for all the cores to access memory without waiting.
The SAME is true for Core 2 Duo (C2D). With half the cores of Kentsfield, the two cores on C2D have PLENTY of FSB and memory bandwidth to run without having to wait on memory requests. Even on laptops that run slower front side buses to keep heat and power usage down.
The same is NOT true for Athlon X2 based systems. Why?
There are 2 reasons why:
1) Core 2 Duo has a MUCH bigger CPU cache (up to 4MB L2, vs. 1MB L2 total in the Athlon). This allows the CPU to store the most used bits of data right where it needs it instead of accessing memory. This is like having the grocery store next to your house, instead of having to hop on a congested highway to drive 10 miles to go get food. Larger caches mean fewer memory accesses, which cuts down on the amount of memory bandwidth that you actually NEED.
Second, the Core 2 Duo has an INCREDIBLY efficient cache prefetcher. What does this mean? Based upon usage patterns, the CPU actually guesses what you are going to need from memory and goes and gets it and stores it in the cache BEFORE you need it. Sometimes it is wrong, or can't fit everything in the cache and has to go to memory anyway, but it means that it is accessing memory when you are not utilizing it as much to be more efficient. This also drastically cuts memory utilization.
Both of these make memory utilization in C2D MUCH lower and is why you see MINIMAL improvement by going from single channel to dual channel memory in these systems. A single stick of 533MHz memory provides almost ALL the memory bandwidth needed for both cores, at least for the slower running desktop processors.
This is why, until laptops CPUs get over 3GHz or you start seeing RAM drives come back in style that increasing the FSB on Core 2 Duo laptops is going to have minimal effect.
Now, if they increase the FSB AND start selling quad core chips for laptops, that is a TOTALLY different discussion. At that point, getting above 667MHz FSB will be useful.
Posted: Mon Jan 15, 2007 2:53 pm
by RonS
I'm going to jump in this pool of lava at the risk of being burned by the flames.
I just read this whole thread twice. It seems like Austin, Brent and Piano are all making valid points. Brining it back to just the T60... If I understand what everyone is saying, then here's my summary in very basic terms:
1. If you're using single-channel 533 memory then the hardware performance is slightly limited, because the FSB runs at 677.
2. If you're running dual-channel 533, then the hardware bottleneck is now shifted to the FSB, because the limit is still 677.
3. None of that matters much in real-world terms, because the CPU memory cache controller is so good that, relatively speaking, the performance bottleneck imposed by the memory and FSB is minimized.
Posted: Mon Jan 15, 2007 3:00 pm
by brentpresley
RonS wrote:I'm going to jump in this pool at the risk of being burned by the flames.
I just read this whole thread twice. It seems like Austin, Brent and Piano are all making valid points. Brining it back to just the T60... If I understand what everyone is saying, then here's my summary in very basic terms:
1. If you're using single-channel 533 memory then the hardware performance is slightly limited, because the FSB runs at 677.
2. If you're running dual-channel 533, then the hardware bottleneck is now shifted to the FSB, because the limit is still 677.
3. None of that matters much in real-world terms, because the CPU memory cache controller is so good that, relatively speaking, the performance bottleneck imposed by the memory and FSB is minimized.
SPOT ON. Good summary man.
(no flames - and pardon me if I seem testy, my PhD dissertation defense is in 48 hours).
Posted: Mon Jan 15, 2007 5:07 pm
by BillMorrow
brentpresley wrote:
SPOT ON. Good summary man.
(no flames - and pardon me if I seem testy, my PhD dissertation defense is in 48 hours).
so THAT is why the normally pleasant mr. brentpresley had a short fuse and the asbestos gauntlets had to be brought out of storage..!
good thing nonny is apparently not online..
and
another FWIW, if you read the newspapers in the US you will see why the server has been down two times this weekend..
ice storms, snow and sleet do bad things to power distribution grids..