Pinmod x61s L7500 unstability

[chriskirk180]

Well I took one of my rarely used x61s L7500s and did the pinmod, out of the 6 sticks of ram i have, I was able to boot with 2 of them, the rest of them didn't POST. Since Windows 7 crashes after about a minute or two and I got what seemed to be graphics artifacts, I proceeded to spd flash my 800MHz stick to 533. The laptop now boots with it but it's quite unstable. tried cpd flashing various settings but to no avail. Before embarking much further, was hoping anyone here might have experience with this and/or know if I'm dealing with memory issues here or general overheating, potentially within the northbridge? I

[xiphmont]

I'm just getting into BSEL overclocking myself.
It could be the memory. It could be the motherboard. It could be the processor. It could be any combination of the above, including all of them if you're spectacularly unlucky

At what speeds and with what voltages are you trying to run? Also, you said you flashed the memory to PC2-5300-- what were the complete timings of the RAM before flashing, and what exactly did you modify? We can at least eliminate the RAM as a possible source of the instability.

[chriskirk180]

Sorry for the late reply xiphmont, I'm trying this with everything stock (no voltage mod, etc..) except for the cut trace. The 800MHz stick wouldn't POST before doing any flashing but another stick of 667 or 533 did POST and ran (although unstable). I tried inputting exactly what the guy over at http://thinkwiki.de/Mehr_Power_f%C3%BCr ... nkl_Tablet used even though the timings didn't come out the same. I also tried increasing settings to get the same end timings he got in the linked table. Failing to get those stable, I then tried 2 spd setting files i found for 16-chip crucial 533 and 667. In the end the above 4 flashes all booted but were unstable under load.

Perhaps the timings are still bad? CPU-Z reports the processor running at 1.6GHz (stock) but Linux /proc/cpuinfo showed it at 2.29 (or 2.19 I forget now). I disabled all cpu power mgmt from BIOS as well to basically force it to "performance-oriented" settings.

[wileE]

You should leave the CPU power managment in the BIOS on automatic. You can even set Scheme on AC to balanced.
Can you get your hands on some Kingston Value Ram 667? They often work well without any changes.

[xiphmont]

Perhaps the timings are still bad? CPU-Z reports the processor running at 1.6GHz (stock) but Linux /proc/cpuinfo showed it at 2.29 (or 2.19 I forget now). I disabled all cpu power mgmt from BIOS as well to basically force it to "performance-oriented" settings.

It's possible when you booted it to Win it was 1.6, and under linux it was 2.15. One aspect of the German instructions appears to be incorrect-- although some motherboards reliably detect pin 7 as being at ground after lifting/cutting the trace, others do not. My batch of 16 was about evenly split between mobos that reliably booted at FSB266 with the cut trace, and mobos that either booted at FSB200 or would go back and forth. Pin 7 really needs to be tied to ground to get a reliable FSB266 boot on all mobos.

Also, the RAM timings on the German site are kinda half-and-half and don't really explain what's going on (though I suppose it's reasonable to expect you to know what you're doing before messing with a mobo Hopefully *I* have this completely right before going off and soundling like some kind of authority on the subject (I'm not)...

There are two almost independent aspects to the DDR2 RAM timings; the pipeline clock speed (what we usually mean by saying 'DDR2-666' or 'DDR2-800') and the actual, physical latencies of the various RAM operations. The physical limits, eg, your Tras, Trc, Twr, etc, are the same at any pipeline speed. The numbers you see like '5-5-5-15' are the result of converting these timings to numbers of pipeline clock cycles at a given operating frequency (rounded up). They're not the real, specified, first-order RAM timings, at least not in DDR2. They're calculated.

The one expection is the column address strobe latency (CL, the first number in that string)) which unlike all the others really is expressed in clock cycles. DDR2 SPDs support up to three different CL timings in a bitmap. Each CL has associated with it a Tclk (in fractional nanoseconds). That Tclk is what sets the pipeline speed, eg, 'DDR2-667'. So CL and Tclk go together and are different for / tied to each supported DDR2 speed. One last oddball, Tac, is also set (in nanoseconds) for each CL. The rest of the timings are always the same for a given stick of RAM regardless the DDR2 speed.

When running the FSB at 133% nominal speed, we have to account for that in all the timings, not just the pipeline clock. Eg, DDR2-800 SDRAM will run the pipeline at a supposed 666MHz (since that's the fastest Santa Rosa supports) *1.333 (for our FSB overclock) == 888MHz, which doesn't sound too bad, only +12%. *but* all the other timings, set in nanoseconds, will really be running at +33% regardless of pipeline speed. So to be absolutely safe, you also need to correct each one of the fixed timings up by a third. (That also means simply flashing timings from a DDR2-666 or DDR2-533 stick won't do it since the fixed timings really have nothing to do with the pipeline speed).

The vast majority, maybe even all DDR2 RAM doesn't really need them all changed like that. For purposes of being sure though, you should do them all. Once that variable is eliminated, you can tweak 'em way back up.

....and if you _do_ happen to run across 4GB sticks that are sound at unmodified DDR2-1066-equivalent timings, let me know! I'm looking! (Closest I've gotten are the DDR2-800 Elpidas with the big black heatspreaders. Unmodded, they throw one error in maybe every five full runs of memtest86+) Oddly, I've got a bunch of 2GB sticks that will do it fine, but no 4GB...

[el-sahef]

When running the FSB at 133% nominal speed, we have to account for that in all the timings, not just the pipeline clock. Eg, DDR2-800 SDRAM will run the pipeline at a supposed 666MHz (since that's the fastest Santa Rosa supports) *1.333 (for our FSB overclock) == 888MHz, which doesn't sound too bad, only +12%. *but* all the other timings, set in nanoseconds, will really be running at +33% regardless of pipeline speed. So to be absolutely safe, you also need to correct each one of the fixed timings up by a third.

This is exactly what I did in the SPD profiles that are in this thread for flashing. However, as different RAM sticks may differ in some timings, there is still the possiblity that some other RAM sticks will not work stable with those profiles, so you still have to check that. But most RAM sticks should work with these.

If not, then the timings of the original profile from those sticks have to be changed manually.

[xiphmont]

This is exactly what I did in the SPD profiles that are in this thread for flashing. However, as different RAM sticks may differ in some timings, there is still the possiblity that some other RAM sticks will not work stable with those profiles, so you still have to check that. But most RAM sticks should work with these.

Ah, excellent. Prebuilt universal download-and-flash SPDs are something I'd wanted when I got started (at least for testing).

Well, I also wanted a more complete explanation of how it all worked so I could understand what I was doing too

[chriskirk180]

Thanks all for the info, I haven't had a chance to play with it yet but the SPD profiles I flashed were the same ones el-sahef posted but none worked. I'll first try to re-enable dynamic cpu settings in the bios then failing that: xiphmont, I'll try upping all params by 33% as you mentioned to see if that helps. Thanks again for all the feedback and thanks xiphmont for the background on the timings!

[el-sahef]

What voltage does CPU-Z show when the CPU is at full load (e. g. prime95)?

[chriskirk180]

I'm really sorry for the late reply, I got swamped with work and other affairs so wasn't able to respond. As I mentioned previously, I disabled all power mgmt in the X61s' BIOS and got tons of graphics artifacts just booting into Windows 7. When launching chrome even, the computer would just BSOD. At the recommendation of this thread, I re-enable all power mgmt to sane "defaults" and I'm happy to say that with my SPD flashed DIMM, it seems to be running stable, and I suppose that since I have a middleton bios, I'm now getting 266MHz fsb @ 4-9 multiplier!! This yields 1064Mhz to 2393Mhz depending on what the governor sees fit. My VID seems to switch between 0.85 to 1.125V. Truly incredible and I have you guys to thank for not only tipping me off with the idea of doing this in the first place but to also get this baby stable. Also, in reply to

So without further ado, any recommendation on me trying it one of my X61's (read: not X61s)? I have a 2.1Ghz, 2.4GHz and 2.2GHz sitting here looking pretty. I read the L7500's have the most success but haven't read too much about 2.2's or the other ones I have in my inventory.

Cheers

[chriskirk180]

Not sure if anyone's seen this before but cpu-z in windows 7 clearly shows up to 2.4GHz but /proc/cpuinfo shows 1.6GHz, is there another tool that can show the real cpu speed?

[wileE]

So without further ado, any recommendation on me trying it one of my X61's (read: not X61s)? I have a 2.1Ghz, 2.4GHz and 2.2GHz sitting here looking pretty.

Do not do the pimod on those boards by cutting the trace. Rather desolder Pin 7. And if you cannot solder anything that small: forget it.
You are very likely to have problems with the required voltage with those CPU.

[xiphmont]

Do not do the pimod on those boards by cutting the trace. Rather desolder Pin 7. And if you cannot solder anything that small: forget it.

I'm generally worried about damaging the pin irreparably more than cutting the trace (I have no idea how much flexing it can take, as desoldering it also requires lifting, and it would need to be tied to ground via a wire for a reliable boot on many mobos anyway... that lever arm on a dangling pin worries me!)

On all my boards, I cut the trace and added a 30ga wire to pin 7 that I could tie to to ground or logic high through a 10K resistor. A permanent modification, yes, but also functionally reverses the cut trace if needed, and relatively easy.

[wileE]

but also functionally reverses the cut trace if needed, and relatively easy.

How? Please describe.

[xiphmont]

but also functionally reverses the cut trace if needed, and relatively easy.

How? Please describe.

I think the easiest way is probably just to tie pin 7 and 8 together. That will pull pin 7 high and set the FSB back to 200. It doesn't actually restore the trace or reconnect pin7 to the Crestline or CPU... but I don't think the logic level on that line ever varies from high anyway (could be wrong!)

If you want to add a switch to set either FSB 200 or 266, here's one possibility: https://people.xiph.org/~xiphmont/think ... switch.jpg <- large pic warning!

In the above pic, the upper wire is going to a ground, the middle to pin 7, and the lower wire to a testpoint that connects to pin 8 (which itself is tied to VCC3B through a 10K resistor). The switch is crazyglued to a piece of scotch tape laid on top of the board; up is 266, down is 200. You can't see it, but the trace from pin 7 is cut (it's obscured by the wire soldered to the testpoint).

[wileE]

Thank you. Going to try that switch.
Although I think I will run out of places to put all my added switches.

[wileE]

Tried the switch. Does not work. FSB stays at 266 when pin 7 & 8 are tied together.

Soldering is ok, checked switch with multimeter. Any suggestions?

[xiphmont]

Tried the switch. Does not work. FSB stays at 266 when pin 7 & 8 are tied together.

Soldering is ok, checked switch with multimeter. Any suggestions?

Got any way to take a high-magnification macro photo? Did you verify voltage levels or just continuity?

[wileE]

Working now. The soldering needed some cleaning. Put these nice switches in both overclocked machines.

[mEon]

Hello,

can you tell what soldering or where the soldering had to be cleaned?

I actually got problems by applying the pinmod at X61 with T7300. Ubuntu / Kernel 3.13:

Code: Select all

CPU 1: Machine Check Exception: 4 Bank 1: .....
TSC ......
PROCESSOR 0:6fb TIME ..... SOCKET 0 APIC 1 microcode ba
Run the abov through 'mcelog --ascii'
CPU 1: Machine Check Exception: 4 Bank 1: .....
TSC ......
PROCESSOR 0:6fb TIME ..... SOCKET 0 APIC 1 microcode ba
Run the abov through 'mcelog --ascii'
CPU 0: Machine Check Exception: 5 Bank 5: -----
RIP !INEXACT! 10:<ffffffff81043cef> {acpi_processor_ffh_cstate_enter ...}
TSC ......
PROCESSOR 0:6fb TIME ..... SOCKET 0 APIC 1 microcode ba
Run the abov through 'mcelog --ascii'
Machine check: Processor context corrupt

Kernel panic - not syncing: Fatal machine check
Kernel Offset: 0x0 from 0xffffffff81000000 (relocation range: ..... - .....)
drm_kms_helper: panic occured, switching back to text console
Rebooting in 30 seconds..

But the ram works fine within a pinmodded X60S with L7500 processor.
The mod worked, sometimes Windows 7 / 64 boots, cpu-Z shows correct parameters :-\

Best regards!