Firstly the CN100 appears to expose the pins on the spi hidden under the magnesium frame.
Soldering the appropriate flex connector may enable us to streamline the flashing for development.
Secondly QM77 provides 8 pcie Lanes of which four are in use,
I'm guessing one of those is eaten up by the Gbit lan controller and it's half speed nonsense.
One goes to the sdcard reader which can be moved to a USB bus with the appropriate controller.
What I would like to look into is the feasibility of building a slice to sit inbetween the QM77 and the system board,
Passing the used pins 1:1 while drawing out the 4 pcie lanes.
System board < Slice < QM77
Next to the USB port on the back there might be space to mount a usb-c connector,
The thunderbolt controller goes onto the daughter "slice" card.
It's only pcie 2.0 but four lanes with tb3 on top of everything else would be impressive and lengthen the lifespan of the system.
The design I have doesn't seem to be the final version of the board,
Do we have access to the final revision?
Do we have the "Intel Platform design guide"
In the Kendo-4 WS from Wistron they reference it with a "Please see Doc No 29635"
Can't have too many 30's.
where CRB = Customer Reference Board
No idea about the rest.
soo for the CN100 the connector is:
and the pins:
For the Schematics and Datasheets:
https://drive.google.com/drive/folders/ ... sp=sharing
The only complain i have with this laptop is the lack of thunderbolt... and TN screen...
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