Coreboot on the X210

[mjg59]

Hi! I've just finished a first attempt at a port of Coreboot (www.coreboot.org) to the X210. For those who are unaware, Coreboot is a (mostly) open source firmware implementation that replaces the system firmware. I'm running it as my primary firmware now, and it boots Linux happily but probably wouldn't work so well with Windows at the moment. The source code is at github.com/mjg59/coreboot, but please bear in mind that making any kind of mistake during the build or flash process (such as not including the embedded controller firmware) will render your machine unbootable and you'll need additional hardware to recover it. This is primarily something I've done for my own interest, but if anyone else is enthusiastic about running it I'll see if I can make some binaries available and provide instructions for flashing it.

[flyingfishfinger]

Very nice project!

Personally I'd be more interested in an X62 variant, but I wish you the best with the completion of this one. Can't help you test due to lack of X210 though, sorry.

R

[tadfisher]

Very cool! I'd love binaries as building coreboot is quite involved if the distribution doesn't provide the build infrastructure for it (e.g. NixOS).

[mjg59]

I'll post binaries shortly - I'm just trying to track down an issue where everything works fine on my machine but wlan doesn't show up on another (nominally identical) board.

[jlee]

Wow. this is pretty cool. How's battery life comparing coreboot to the default bios?

[L29Ah]

Do you plan pushing it to the upstream?

[flyingfishfinger]

What flash chip is used on the X210?

R

[mjg59]

The issue with the wifi card turned out to be mechanical. I'm in the process of rebasing this on current upstream and will post some binaries once I'm done.

[mjg59]

Ok, uploaded stuff to https://github.com/mjg59/coreboot/releases/tag/x210_1.0 - the coreboot.rom image there can be flashed directly using Flashrom with current git:

sudo flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom

Note that, as the argument suggests, this might go horribly wrong and you'll need an external programmer to rescue you. If you build from source, no matter what you do ensure that you include the embedded controller firmware otherwise the machine will end up completely broken and very hard to re-flash. The blobs.zip file contains the device-specific binaries that are required during the build.

This image will give you a UEFI system with no BIOS support. It boots Linux fine - I have no idea whether it will boot Windows. I've only tested this with a batch 2 device, I don't know what it'll do on batch 1 boards given the SATA/NVMe issues. Batch 3 boards seem to use the same firmware as batch 2, so maybe that'll work, but don't blame me if it doesn't.

[skx]

Ok, uploaded stuff to https://github.com/mjg59/coreboot/releases/tag/x210_1.0 - the coreboot.rom image there can be flashed directly using Flashrom with current git:

sudo flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom

WARNING: do not internal flash your device with stock bios as I will rather sooner than not end up in a non booting machine and if you do not have a dump of your bios it will be a paper weight. internal flashing only works as soon as you did your initial coreboot flash with external flasher

mjg59: how did you flash your initial flashed coreboot rom? external flashing, right?

[mjg59]

No, this machine has never had an external flasher connected (we did the initial port on another machine and did use a flasher there). I've switched between stock and coreboot several times using -p internal.

[mjg59]

(Oops, duplicate)

[harryK]

Ok, uploaded stuff to https://github.com/mjg59/coreboot/releases/tag/x210_1.0 - the coreboot.rom image there can be flashed directly using Flashrom with current git:

sudo flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom

Note that, as the argument suggests, this might go horribly wrong and you'll need an external programmer to rescue you. If you build from source, no matter what you do ensure that you include the embedded controller firmware otherwise the machine will end up completely broken and very hard to re-flash. The blobs.zip file contains the device-specific binaries that are required during the build.

This image will give you a UEFI system with no BIOS support. It boots Linux fine - I have no idea whether it will boot Windows. I've only tested this with a batch 2 device, I don't know what it'll do on batch 1 boards given the SATA/NVMe issues. Batch 3 boards seem to use the same firmware as batch 2, so maybe that'll work, but don't blame me if it doesn't.

Ok, I got impatient and built coreboot from your source with vladislav's modified ec.bin from viewtopic.php?p=833699#p833699, added seabios as payload, flashed my third batch machine and now it doesn't boot

It is not completely dead: the battery is charging, the status lights work and correctly signal whether ac is attached, but if I press the power button the screen stays off and I don't think that anything is happening.

I have a backup of the stock bios and a SOIC8 clip, so I should be able to rescue it. Here's my .config https://pastebin.com/NaXYfZiP. Any idea of what I could be missing in my build?

[mjg59]

First boot after reflashing may take up to a minute for RAM link calibration - how long did you wait?

[mjg59]

But also you have:

+# CONFIG_DRIVERS_PS2_KEYBOARD is not set

which is definitely a problem You probably also want

CONFIG_RUN_FSP_GOP=y

if you're running Tiano as a payload, along with:

CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y

I basically haven't tested SeaBIOS as a payload, so things could definitely be weird in that respect.

[harryK]

But also you have:

+# CONFIG_DRIVERS_PS2_KEYBOARD is not set

which is definitely a problem You probably also want

CONFIG_RUN_FSP_GOP=y

if you're running Tiano as a payload, along with:

CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y

I basically haven't tested SeaBIOS as a payload, so things could definitely be weird in that respect.

Hi Matthew,

I saw that you committed some changes to the repo in the last few days and gave it another go at building it from your x210_test branch with Vladislav's patched EC. All seems to be working well on batch three, bar a couple of glitches.

1. ASPM L1 substates are not enabled. The PCI root ports don't show the capability at all

***** EDIT ******
L1 substates can be enabled turning on support for the esoteric ClkReqNumber in devicetree.cb The following configuration works:

Code: Select all

register "PcieRpEnable[2]" = "1"
	register "PcieRpClkReqSupport[2]" = "1"
	register "PcieRpClkReqNumber[2]" = "0"
	register "PcieRpClkSrcNumber[2]" = "0"
	register "PcieRpAdvancedErrorReporting[2]" = "1"
	register "PcieRpLtrEnable[2]" = "1"

	register "PcieRpEnable[3]" = "1"
	register "PcieRpClkReqSupport[3]" = "1"
	register "PcieRpClkReqNumber[3]" = "1"
	register "PcieRpClkSrcNumber[3]" = "1"
	register "PcieRpAdvancedErrorReporting[3]" = "1"
	register "PcieRpLtrEnable[3]" = "1"

	register "PcieRpEnable[8]" = "1"
	register "PcieRpClkReqSupport[8]" = "0"     # L1 substates have to be switched off for the nvme port. No drive ever booted if active. Tried several clkreq numbers.
	register "PcieRpClkReqNumber[8]" = "2"
	register "PcieRpClkSrcNumber[8]" = "2"
	register "PcieRpAdvancedErrorReporting[8]" = "1"
	register "PcieRpLtrEnable[8]" = "1"

2. Another strange thing is that the processor seems to have lost support for Energy performance bias:

Code: Select all

# x86_energy_perf_policy power
x86_energy_perf_policy: EPB not enabled on this platform

Setting HWP policy works though.

Anyway, power consumption doesn't seem to be suffering. The machine idles at 3.2W with brightness 5/15.

3. One annoying bug is that the machine seems to turn on whenever a power source is attached.

4. Linux ME module doesn't seem to be playing well with the ME, however I disabled it in the stock bios, so I don't know if this was also the case before.

Code: Select all

mei_me 0000:00:16.0: wait hw ready failed
[    7.234911] mei_me 0000:00:16.0: hw_start failed ret = -62
[    7.234919] mei_me 0000:00:16.0: H_RST is set = 0x80070731
[    9.250907] mei_me 0000:00:16.0: wait hw ready failed
[    9.250910] mei_me 0000:00:16.0: hw_start failed ret = -62
[    9.250918] mei_me 0000:00:16.0: H_RST is set = 0x80070731
[   11.266907] mei_me 0000:00:16.0: wait hw ready failed
[   11.266911] mei_me 0000:00:16.0: hw_start failed ret = -62
[   11.266915] mei_me 0000:00:16.0: reset: reached maximal consecutive resets: disabling the device
[   11.266917] mei_me 0000:00:16.0: reset failed ret = -19
[   11.266918] mei_me 0000:00:16.0: link layer initialization failed.
[   11.266920] mei_me 0000:00:16.0: init hw failure.
[   11.266966] mei_me 0000:00:16.0: initialization failed.

Hope this helps!

[mjg59]

L1 substates can be enabled turning on support for the esoteric ClkReqNumber in devicetree.cb The following configuration works:

Thanks! I'll merge that.

2. Another strange thing is that the processor seems to have lost support for Energy performance bias:

Huh weird. There's presumably some setup required that Coreboot's not doing - I'll look into that.

3. One annoying bug is that the machine seems to turn on whenever a power source is attached.

There's a Coreboot config option for what should happen when power is attached, try switching that?

4. Linux ME module doesn't seem to be playing well with the ME, however I disabled it in the stock bios, so I don't know if this was also the case before.

Hmm, I don't see those errors - did you use a fresh ME image, or did you extract your existing one? I'm not an ME expert, so not sure why that might happen (although I think I did see the same at some point)

[mjg59]

2. Another strange thing is that the processor seems to have lost support for Energy performance bias:

Huh weird. There's presumably some setup required that Coreboot's not doing - I'll look into that.

darn Intel. https://review.coreboot.org/c/coreboot/+/34458 should fix that.

[harryK]

2. Another strange thing is that the processor seems to have lost support for Energy performance bias:

Huh weird. There's presumably some setup required that Coreboot's not doing - I'll look into that.

Your patch makes the trick. Thanks!

3. One annoying bug is that the machine seems to turn on whenever a power source is attached.

There's a Coreboot config option for what should happen when power is attached, try switching that?

There's no obvious option in menuconfig. Do you have an idea of what that could be?

Also, cold boot is very slow. I have

Code: Select all

$systemd-analyze
Startup finished in 32.368s (firmware) 

whereas reboot is instant. It's as if it does the memory training bit every time

[flyingfishfinger]

Slightly OT: After nearly 4 months of bothering Jacky on WeChat my X210 full machine is finally in the mail !

Can't wait to play with the goodies in this thread

[verynice]

Is it possible to add fn+ctrl swap?
Also, could https://github.com/harrykipper/x210
coreboot.rom image be updated with latest changes, please.
And the last one, has anyone tried the libgfxinit (there are
some pending patches, but still)?

[harryK]

Is it possible to add fn+ctrl swap?
Also, could https://github.com/harrykipper/x210
coreboot.rom image be updated with latest changes, please.
And the last one, has anyone tried the libgfxinit (there are
some pending patches, but still)?

Hi,
I updated the coreboot image syncing it with the latest coreboot source, which contains Matthew's patch to enable EPB. I also enabled SATA ALPM and Dev Sleep and a couple of other things for power saving, and included the latest CPU microcode from Intel. BTW note that this version of coreboot sets the TDP to 25W / 44W. It should also be possible to undervolt the processor, but I don't know how Also, I don't know how to change the keyboard mapping. Sorry, I am still learning..

Please be careful when flashing and have a backup and hardware flasher at hand in case things go wrong.

[verynice]

Is it possible to add fn+ctrl swap?
Also, could https://github.com/harrykipper/x210
coreboot.rom image be updated with latest changes, please.
And the last one, has anyone tried the libgfxinit (there are
some pending patches, but still)?

Hi,
I updated the coreboot image syncing it with the latest coreboot source, which contains Michael's patch to enable EPB. I also enabled SATA ALPM and Dev Sleep and a couple of other things for power saving, and included the latest CPU microcode from Intel. BTW note that this version of coreboot sets the TDP to 25W / 44W. It should also be possible to undervolt the processor, but I don't know how Also, I don't know how to change the keyboard mapping. Sorry, I am still learning..

Please be careful when flashing and have a backup and hardware flasher at hand in case things go wrong.

I get programmer error when I try flashrom -p internal -w from the old coreboot.rom

[harryK]

Hi,
I updated the coreboot image syncing it with the latest coreboot source, which contains Matthew's patch to enable EPB. I also enabled SATA ALPM and Dev Sleep and a couple of other things for power saving, and included the latest CPU microcode from Intel. BTW note that this version of coreboot sets the TDP to 25W / 44W. It should also be possible to undervolt the processor, but I don't know how Also, I don't know how to change the keyboard mapping. Sorry, I am still learning..

Please be careful when flashing and have a backup and hardware flasher at hand in case things go wrong.

I get programmer error when I try flashrom -p internal -w from the old coreboot.rom

you need

Code: Select all

flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom

[verynice]

This is great release, but...
I can't boot my nvme drive:
DMAR-IR: [Firmware Bug]: ioapic has no mapping iommu, interrupt remapping will be disabled
DMAR: Failed to create 0-16MiB identity map
nvme DMAR: allocating domain failed

[harryK]

This is great release, but...
I can't boot my nvme drive:
DMAR-IR: [Firmware Bug]: ioapic has no mapping iommu, interrupt remapping will be disabled
DMAR: Failed to create 0-16MiB identity map
nvme DMAR: allocating domain failed

Strange. Try booting with intel_iommu=off maybe?
Also, I just realised that I killed the ME with me_cleaner in this release, that could be related to the issue. I'll reupload the image with the full ME in a bit.
FWIW everything works well for me with the deactivated ME, but I don't enable IOMMU and DMAR in my kernel

[verynice]

This is great release, but...
I can't boot my nvme drive:
DMAR-IR: [Firmware Bug]: ioapic has no mapping iommu, interrupt remapping will be disabled
DMAR: Failed to create 0-16MiB identity map
nvme DMAR: allocating domain failed

Strange. Try booting with intel_iommu=off maybe?
Also, I just realised that I killed the ME with me_cleaner in this release, that could be related to the issue. I'll reupload the image with the full ME in a bit.
FWIW everything works well for me with the deactivated ME, but I don't enable IOMMU and DMAR in my kernel

I'd like to boot with iommu as i use iommu for device pass through and virtualization.
I don't think that ME is related, I think it's one of the changes in the policies.

[flyingfishfinger]

Hi,
I updated the coreboot image syncing it with the latest coreboot source, which contains Matthew's patch to enable EPB. I also enabled SATA ALPM and Dev Sleep and a couple of other things for power saving, and included the latest CPU microcode from Intel. BTW note that this version of coreboot sets the TDP to 25W / 44W. It should also be possible to undervolt the processor, but I don't know how

Wow this sounds awesome! Have Matthew's changes been merged into coreboot master? His own Github master latest is 3 months old...

Since I want to build my own version with SeaBIOS & Tinycore Linux as a payload (!), can you give some tips as to what specific power saving things you've enabled and how to do the Intel microcode update? I've done a build of coreboot before but not to this level of customization so might need some guidance here.

Unless they're named differently in Menuconfig, the actual .config file makes no mention of Dev Sleep and ALPM, for example. Where are these options usually configured?

Thanks,
R

[mjg59]

Is it possible to add fn+ctrl swap?

No, that's a function of the embedded controller, which is still running proprietary firmware.

And the last one, has anyone tried the libgfxinit (there are
some pending patches, but still)?

libgfxinit works for cold boots, but fails to reinitialise the screen on reboots. I'm working with the maintainer to try to figure that out.

[mjg59]

Wow this sounds awesome! Have Matthew's changes been merged into coreboot master? His own Github master latest is 3 months old...

https://review.coreboot.org/c/coreboot/+/32531 is the ongoing review.