P7 CPU Chip WARNING -- MANY PHOTOS

[Takeda]

While working for IBM, I developed, and taught a semiconductor (microelectronics) course. One of my "show and tells" was a P7 CPU chip (wafer, and modules). The P7 was developed by IBM in 2009, using a 45nm (nanometer) technology. 45nm is the minimum feature size (poly width) for the chip design. The P7 successor is the P8 CPU.

Here are some photos, that I thought would be of interest. The DOF is extremely shallow in some of the photos, even at f/22.


1 300mm silicon wafer. Red rectangle is one of many P7 CPU chips on the wafer.
http://bob-ayers.smugmug.com/Other/IBM- ... 001-XL.jpg


2 Closer image of P7 CPU chip.
http://bob-ayers.smugmug.com/Other/IBM- ... 002-XL.jpg


3 P7 CPU chip size comparison to penny.
http://bob-ayers.smugmug.com/Other/IBM- ... 003-XL.jpg


4 Magnified edge of P7 CPU chip.
http://bob-ayers.smugmug.com/Other/IBM- ... 004-XL.jpg


5 Magnified edge of P7 CPU chip.
http://bob-ayers.smugmug.com/Other/IBM- ... 005-XL.jpg


6 Eye of needle used for size reference. Spherical shapes are solder balls used for I/O, power, and ground connections to chip.
http://bob-ayers.smugmug.com/Other/IBM- ... 006-XL.jpg


7 Black rectangle is backside of “diced” chip attached to ceramic substrate. Chip solder balls are reflowed to attach chip to ceramic substrate.
http://bob-ayers.smugmug.com/Other/IBM- ... 007-XL.jpg


8 Edge of ceramic substrate.
http://bob-ayers.smugmug.com/Other/IBM- ... 008-XL.jpg


9 Bottom of ceramic substrate. Gold pads are for chip connections to socket/card.
http://bob-ayers.smugmug.com/Other/IBM- ... 009-XL.jpg


10 Top of completed module.
http://bob-ayers.smugmug.com/Other/IBM- ... 010-XL.jpg


11 Edge of completed module.
http://bob-ayers.smugmug.com/Other/IBM- ... 011-XL.jpg


12 Bottom of completed module.
http://bob-ayers.smugmug.com/Other/IBM- ... 012-XL.jpg

Admin edit: Changed all huge inline images to links. Please keep any image to <50KB; i.e., post a thumbnail as a link to the full image

[Temetka]

Awesome.

Why use a circular wafer? Seems a lot is lost in the die cutting process.

[Takeda]

Awesome.

Why use a circular wafer? Seems a lot is lost in the die cutting process.

Good question!

The wafer comes from a "slice" of a semiconductor cylinder. The cylinder is "pulled" while spinning from molten semiconductor material, which makes it round. After the cylinder is made, it is sliced into wafers, which are lapped, and polished. Also, with a round wafer, handling through the chip fabrication process is a lot easier.

[Temetka]

I've seen a few video's on how CPU's are made. I understand the whole giant silicon crystal and how it's pulled. I was just curious if it's the most efficient way to do it. It seems to me that a lot of silicon material around the edges goes to waste. But then again it's easier to spin the doping chemicals on to the substrate as a circle than a square or rectangle. Thanks for answering though.

[BillMorrow]

interesting presentqation.. thanks..

for the waste question one would initially think, good question but with more thought i'll bet intel and ibm et al., already thought of that and decided the waste of a cylindrical semiconductor "mother chunk" outweighs handling costs and so forth..
but this is only a guess..

all in all, quite educational..

[Temetka]

I thought about that as well, Bill. I also came to the same conclusion you did. I am pretty sure they spent some time and research coming up with the optimal shape for the silicon wafer. I know I would if I was doing stuff like that.

[Takeda]

interesting presentqation.. thanks..

for the waste question one would initially think, good question but with more thought i'll bet intel and ibm et al., already thought of that and decided the waste of a cylindrical semiconductor "mother chunk" outweighs handling costs and so forth..
but this is only a guess..

all in all, quite educational..

Thanks Bill!