#2
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by rkawakami » Mon May 18, 2015 2:29 am
From a memory testing point of view this is indeed an old problem made new again due to the usage of smaller geometries in the design of memory cells. I've written some memory test patterns in the past that have done this "hammering", however in order to be truly effective, one needs to know the physical layout of the memory array. I believe that all of the DRAM and SRAM designs that I've been involved in testing over the last 35 years have always scrambled the order of the row and/or column addresses.
To put it briefly, the electrical (also called logical) address (that which is applied to the input pins of the memory device) is not the same as the physical address of where that row is located in the array. In other words, logical row address 0 is not always physically located next to logical row address 1. This is the due to the way how the layout designers construct the memory array. One of the favorite techniques is to construct a sequence of physical rows but "flip" them for the next section. So if the first 4 logical rows are physically laid out in a 0, 2, 3, 1 sequence, then the next four will be 6, 4, 5, 7.
However, if the intent of this hammering is to simply alter (corrupt) data located elsewhere in the memory array, then one doesn't really need to know the logical-to-physical translation.
Running this type of disturb data pattern can add several seconds to the overall test time when the memory chip or module is being tested before leaving the factory. It would also tend to increase the cost of the memory as added test time means added cost to whoever is buying the product.
Ray Kawakami
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