Excellent Merom/Conroe processor preview

[K. Eng]

link

The interesting thing about this review is that it directly compares a 4MB cache and 2MB cache part. Bottom line is that in games, the 4MB cache makes a big difference. However, for most people, the 2MB part packs more than enough punch.

[hdahl]

You don't think that the case is that a 4MB cache for a 64 bit machine and a 2MB cache for a 32 bit machine may both store exactly the same number of words and therefore it may cache exactly the same amount of data (excluding some things which do not double when the number of bits per word is doubled)?

Best regards,

Henrik Dahl

[christopher_wolf]

You don't this that the case is that a 4MB cache for a 64 bit machine and a 2MB cache for a 32 bit machine may both store exactly the same number of words and therefore it may cache exactly the same amount of data (excluding some things which do not double when the number of bits per word is doubled)?

Best regards,

Henrik Dahl

Huh?

Oh, did you mean "You don't think that [...]?"

[K. Eng]

A CPU's ability to address 64-bit addresses shouldn't have a hugely negative impact on code density, though there is some hit.

Remember that 64-bit refers to addresses, not word or field length. I'm not up to date on x86/x64, but 64-bit doesn't mean that everything suddenly takes up 2x the space!

You don't think that the case is that a 4MB cache for a 64 bit machine and a 2MB cache for a 32 bit machine may both store exactly the same number of words and therefore it may cache exactly the same amount of data (excluding some things which do not double when the number of bits per word is doubled)?

Best regards,

Henrik Dahl

[hdahl]

I obviously agree with you that if the next generation of processor is just a processor which can address using 64 bit for the address, then it does not have the impact on the basic "word size" of the processor. I just thought it was a 64 bit processor we were going to see and if that's the case 64 bit as with 32 bit as with 16 bit as with 8 bit refers to exactly the word size and nothing but that. The addressing abilities do not have anything to do with the word size or the n factor in n bit processor so to say, except that concrete implementations of processors could indicate a relationship, or processor sales people perhaps.

You may for instance read here: "http://www.viruslist.com/en/glossary?glossid=189207896".


Best regards,

Henrik Dahl

A CPU's ability to address 64-bit addresses shouldn't have a hugely negative impact on code density, though there is some hit.

Remember that 64-bit refers to addresses, not word or field length. I'm not up to date on x86/x64, but 64-bit doesn't mean that everything suddenly takes up 2x the space!

You don't think that the case is that a 4MB cache for a 64 bit machine and a 2MB cache for a 32 bit machine may both store exactly the same number of words and therefore it may cache exactly the same amount of data (excluding some things which do not double when the number of bits per word is doubled)?

Best regards,

Henrik Dahl