QUESTION: PC2700 vs PC3200 RAM

[sojourner]

Does anyone know if a T41 can take advantage of greater FSB speeds possible with PC3200 compared with PC2700?

Thnx

[dr_st]

It can't.

[Bruce Guttman]

Similar question: I know it won't run faster, but can I put in two PC-3200 sticks and have it work? I know the R-40 is supposed to use PC-2100 sticks but IBM now recommends PC-2700 (like the T-4x series). Does a PC-3200 (NOT PC2-3200) work?

[RealBlackStuff]

All those RAM modules are (supposed to be) backwards compatible. A 3200 will work in a 2700 and most likely also in a 2100.
A 2700 will work in a 2100 (and a 3200).
They will run at the speed as defined by the onboard-chipset.
So a 2700 will work at 2100 in a 2100 machine, etc.

[AIX]

They are supoosed to work but sometimes they are not working; so, to be sure, you have to test it first if possible.

[laboye]

In this situation (PC2100 TP w/ PC2700/PC3200 RAM), I usually get problems only if I mix 2 different brand modules. AFAIK, the problem lies the adjustment of the CAS latency when the module is being slowed down. For example, A PC2100 module might operate with a CAS latency of 2ms while a PC2700 or PC3200 module may have a CAS latency of 3ms. When faster modules are slowed down, they reduce their latency to compensate for the drop in bandwidth. Typically, those faster modules will not operate at 3ms if they are slowed down to PC2100 speed. Some of those 3ms modules will drop to 2ms, but others will drop to 1.5ms. If these 2 differently timed modules are in the same system, it will not start.

In short: Are you using 2 different brands/models of DDR modules?

[sjthinkpader]

CAS latency is counted in cycles rather than time.

CAS latency change is not related to drop in bandwidth but the time to get data from storage node to the output buffer doesn't change so much. So at faster (shorter) clock cycles, the RAM needed more clock cycles to get the data to the output buffer. They all need roughly about 12-15 nSec from CAS (column address available) to data on the output buffer. Basically the RAM has to decode the column address, activate the column driver, sense the storage node, drive the output high or low within this period of time. Speed only get faster when the process design rule get smaller or working voltage get lower (such as DDR2, DDR3).

The computer operates at JEDEC standard timing or what the SPD data tells it. If you have two modules of different speed, the data may disappear from the RAM output buffer in one module faster than the computer expects it. This is called not enough HOLD time. If the RAM couldn't get the data there by the time the computer expects it, this is called not enough SETUP time.