Strange connector pad on X41 system board (PIC link)

[Raceboy]

Hi folks!

I noticed as weird connector pad on the underside of the X41 PCB exactly under the HDD connector. It has 28 pins which is much less than 40 like ZIF connector has.

Does anybody have any idea what is it for? On X40 board it is not present.

Here's link to the photo of it: http://www.porsche-foorum.ee/album/albu ... %20ZIF.jpg

I have to look if I can find my X41 complete schematic and see if there's some info in there.

Would be nice if it is a SATA connector so wires could be soldered there directly for SATA conversion

[Raceboy]

Ok, quick research and some digging in schematics gave it as an ITP Connector, whatever that means. If anyone has any idea about its purpose/usefulness etc don't hesitate to scream

Here's a schematic of this connector: http://www.porsche-foorum.ee/album/albu ... X41_J1.jpg

[billp117]

It would be my opinion that it does nothing. It looks like a place on the board for attaching a connector (but not for your model). Since the actual connector was never installed on the board you cannot use it.

[rkawakami]

Given the signal names attached to the connector and where they go to on the rest of the motherboard (clock, reset, CPU), I'd guess that it has to do with system testing. TDI, TMS, TRST, TCK are associated with JTAG Boundary Scan.

[topmahof]

rkawakami, you hit it pretty good. if it had a connector on it it would be a debug port.
1.3.2 JTAG Signal Layout Guidelines
Table 3. JTAG Signal Layout Guidelines
Debug Port Signal Layout Guideline
TCK This is a critical JTAG clock signal, sourced by the debug port, which requires
thorough timing and signal integrity analysis/simulation. The termination
resistor to GND on TCK must be located within 200 ps of the debug port in
order to minimize IR losses that would degrade signal voltage levels at the
loads. The length of TCK should not exceed 2 ns in electrical length. Note that
TCK returns a feedback copy of TCK to FBO at the debug port. The length of
the trace between the processor TCK pin and the debug port must be equal to
the electrical length of BPM[5:0] and RESET# from the processor to the debug
port. Load capacitance at the processor must be no more than 35 pF. It is
strongly recommended that this signal be simulated for signal integrity
purposes. Non-monotonicity on the rising or falling edge of TCK will render the
ITP inoperative. See the Execution Signal Layout Guidelines section of this
chapter for additional information.
TMS Critical JTAG mode select signal, sourced by the debug port, which requires
moderate timing and signal integrity analysis / simulation. The termination
resistor to VTAP on TMS should be located within 200 ps of the debug port in
order to minimize resistive losses that would degrade signal voltage levels at
the loads. TMS is driven on the falling edge of TCK at the ITP and recovered
on the following rising edge of TCK at the processor.
TDI, TDO JTAG scan data signals. These signals require minor timing and signal
integrity analysis / simulation. The terminations should be located within 300 ps
to each load. TDI is driven on the falling edge of TCK at the ITP and recovered
on the following rising edge of TCK at the processor.
TRST# Non-critical JTAG reset signal routed to all scan chain devices. TRST#
requires a pull-down resistor to ensure the signal is held in the asserted (low)
state if the debug port is not driving the signals. Layout of this signal needs to
be such that noise will not be coupled to the signal and cause a false reset of
the scan chain.